1. Field of the Invention
The present invention relates to a memory for storing information in an information processing system and, more particularly, to a multi-word wide memory having multiple word read capability and single word write capability.
2. Description of the Prior Art
All information processing systems include some form of memory for storing information, that is, data and intructions, to be operated upon by the system. For example, in a typical system the data and instructions are written into the memory until required by the system processing elements, are read from the memory to the processing elements to be operated upon, and the results written back into memory. In addition, in many systems the memory is the primary information path through the system. That is, information is usually transferred between two elements of the system, such as a central processing unit and an input/output controller, through the memory. As such, the speed and ease with which information may be read from or written into memory is a primary factor in determining the performance of the system.
In many systems, the speed of the system is increased by making the width of the system memory and system bus a multiple of the basic elements of information used by the system. For example, a system may basically operate on elements of information, referred to as words, which contain 32 bits of information. The system bus and memory may accordingly be two words, or 64 bits, wide so that two words are transferred on each memory read or write operation.
A first limitation on memory performance arises because many operations performed by the system involve the transfer of more information than can be contained within a single width of the system memory or bus. For example, a central processing element may perform a cache fill operation which involves the transfer of four, eight or sixteen words. In the example of the memory and bus described just above, this would require, respectively, two, four or eight memory operations. While the memory and bus widths may be increased to acommodate such operations, this solution is very expensive to implement for very wide memories and busses.
A related problem occurs in memory write operations in that the memory width is not conveniently related to the sizes of most information elements written into memory. That is, many memories are a double word wide and read and write a double word at a time. The system, however, performs most operations on information elements of a word or less in size and as such many write operations are of elements, for example, a word, that are less than a full memory information unit.
The present invention provides a memory structure and operation having improvements and features which address the above described problems and limitations, and others.